Management Data Input/Output (MDIO), or also Media Independent Interface Management (MIIM), is a serial bus defined for the Ethernet family of IEEE 802.3 standards for Media Independent Interface, or MII. The MII connects Media Access Control (MAC) devices with Ethernet physical layer (PHY) circuits.
The MII has two interfaces:
The MDIO bus provides access to the configuration and status registers of each PHY. These registers are used to initially configure each PHY and also to monitor status during operation.
The MAC device controlling the MIIM is also called Station Management Entity (STA).
The MDIO interface is implemented by two lines:
The clock line is driven by the MAC device. The data line is bidirectional: the PHY drives it to provide register data at the end of a read operation.
The bus has a single MAC master, but can have up to 31 PHY slaves.
The MDC clock can be a periodic, with a minimum period of 400 ns, which corresponds to a maximal frequency of 2.5 MHz. Newer chips, however, allow faster accesses.
The MDIO data line has a pull-up of 1.5 kOhm in the PHY, allowing the MAC to determine if one or more PHYs are attached. The MAC should have a 2 kOhm pull-down on that same line.
Before a register access, PHY devices generally require a preamble of 32 ones on the MDIO line.
The accesses are made out of 16 control bits followed by 16 data bits. The control bits specify the access type (read or write), the PHY address and the register address.
During a write command, the MAC provides control and data. In the case of a read command, the PHY takes over the bus at the end of the address cycle and supplies the MAC with the data.
When the MAC drives the MDIO line, it has to guarantee a stable value 10 ns before the rising edge of the clock MDC. Further, MDIO has to remain stable 10 ns after the rising edge of MDC. However, when the PHY drives the MDIO line, its output changes after the rising edge of MDC and is stable before the arrival of the next rising edge.
The "Clause 22" MDIO interface specifies 5 PHY address bits which allows for up to 32 PHY devices on a single MDIO data line, and 5 register address bits which allows up to 32 registers per PHY.
The function of the registers is left free for the manufacturer to specify.
The 802.3ae "Clause 45" interface can access up to 65536 registers in 32 different devices. These features were added for 10 Gigabit Ethernet and use different opcodes and start sequences.
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